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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT TYPE
FUNCTION
DC-AC Inverter Control IC
1ch control with Full-Bridge (For USE FET Body-Di)

Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Striking time can Control independently (STRK pin) Circuit protection with Timer Latch (COMP) Circuit protection with quick Shutdown (COMPSD) Mode-selectable the operating or stand-by mode by stand-by pin Synchronous operating the other BD9270F ICs BURST mode controlled by PWM input Output liner Control by external DC voltage Built-in Error mode output pin (FAIL pin)
Absolute Maximum RatingsTa = 25
Parameter Supply Voltage OUTPUT DRIVER Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation
*
Symbol VCC LNx, HFNx, Topr Tstg Tjmax Pd
Limits 20 20 -40+85 -55+150 +150 688
*
Unit V V mW
Pd derate at 5.5mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Operating condition
Parameter Supply voltage DRIVER frequency Symbol VCC FOUT Limits 8.519.0 30110 Unit V kHz
REV. B
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Electric CharacteristicsTa=25VCC=12VSTB=3.0V
Parameter Symbol MIN. Limits TYP. MAX. Unit Conditions
FOUT=60kHz, FB=GND, DUTY=0V
((WHOEL DEVICE)) Operating current Stand-by current
((STAND BY CONTROL))
Icc1 Icc2 VstH VstL VREG IREG Vvccuvlo Vvccuvlo FOUT VRT RSRT ISS VSS_ST VSS_ED ISTRK VSTRK_ED VIS1 VIS2 VVS IIS1 IIS2 IVS VISCOMP1 VISCOMP2 VREFIN DUTY-th RsinkLN RsourceLN RsinkHFN RsourceHFN MAX DUTY VCP ICP VCOMPH VCOMPH VCOMPSDH VCOMPSDH RFAIL VCT_SYNCH VCT_SYNCL
RSYNC_OUT_sink
RSYNC_OUT_source
2 -0.3 3.92 5 7.0 0.50 63.0 1.05 0.9 0.18 1.35 0.8 1.94 1.225 1.22 40 0.593 0.6 0.90 1.8 4.5 1.8 4.5 44.0 1.94 0.9 1.94 0.05 1.94 0.05 3.8 2.5 -0.3
4.5 30 4.00 7.5 0.60 65.0 1.50 100 1.1 0.20 1.50 1.0 2.00 1.25 VREFIN 1.25 50 0.625 0.50 1.00 3.5 9.0 3.5 9.0 45.5 2.00 1.0 2.00 0.10 2.00 0.10 100 4.0 150 300
8.1 70 VCC 0.8 4.08 8.0 0.70 67.0 1.95 200 1.3 0.22 1.65 1.2 2.06 1.275 VIS1 1.28 0.9 60 0.9 0.657 1.6 1.10 7.0 18.0 7.0 18.0 47.0 2.06 1.1 2.06 0.15 2.06 0.15 200 4.2 0.5 300 400
VCT_SYNCH
mA uA V V V mA V V kHz V uA V V uA V V V V uA uA uA V V V V % V uA V V V V V V V V
Stand-by voltage H Stand-by voltage L ((REF4V BLOCK)) REF4V output voltage
REF4V source current ((VCC UVLO BLOCK)) Operating voltage (VCC) Hysteresis width (VCC)
System System
((OSC BLOCK))
Drive output frequency
RT=18.9k
RT pin voltage SRT ON resistance ((SS STRK BLOCK)) Soft start current
SS operation start voltage
SS term END voltage STRK current
STRK term END voltage ((FEED BACK BLOCK))
IS threshold voltage 1 IS threshold voltage 2 VS threshold voltage IS source current 1 IS source current 2 VS source current
IS COMP detect voltage 1 IS COMP detect voltage 2 VREF input voltage range
VREF applying voltage DUTY=1.5V DUTY=0V, IS=1.0V VREFIN1.25V VREFIN= 1V No effect at VREF1.25V Low = IS high (burst off) VCC=12V VCC=12V VCC=12V VCC=12V FOUT=65kHz
((DUTY BLOCK))
DUTY threshold voltage
((OUTPUT BLOCK))
LN output sink resistance LN output source resistance HFN output sink resistance
HFN output source resistance
MAX DUTY
((TIMER LATCH BLOCK)) Timer Latch setting voltage Timer Latch setting current
((COMP BLOCK))
COMP over voltage detect Hysteresis width (COMP) COMPSD over voltage detect Hysteresis width (COMPSD) VSS1.65V, SRT operate, CP timer latch
VSS1.65V, OSC 2 count
FAIL ON resistance
((SYNCHRONOUS BLOCK)) CT_SYNC_OUT High voltage CT_SYNC_OUT Low voltage
CT_SYNC_OUT sink resistance CT_SYNC_OUT source resistance
CT_SYNC_IN High voltage input range CT_SYNC_IN Low voltage input range
VCT_SYNC_IN_H VCT_SYNC_IN_L
1
This product is not designed to be radiation-resistant.
REV. B
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Package Dimensions
Pin Description
Device Mark
PIN No. 1 2 3 4
PIN NAME PGND LN2 HFN2
CT_SYNC_IN
FUNCTION
Ground for FET drivers NMOS FET driver NMOS FET driver (New Function) CT synchronous signal input pin
BD9270F
5 6 7
CT_SYNC_OUT CT synchronous signal output pin
REF4V SRT RT GND DUTY FAIL STB CP VREF VS IS FB SS STRK COMPSD COMP VCC HFN1 LN1
Internal regulator output External resistor from SRT to RT for adjusting the start-up triangle oscillator External resistor from RT to GND for adjusting the triangle oscillator GROUND Control PWM mode and BURST mode Error mode OUTPUT Pin (open drain) Stand-by switch External capacitor from CP to GND for Timer Latch Reference voltage input pin for Error amplifier Error amplifier input Error amplifier input Error amplifier output External capacitor from SS to GND for Soft Start Control Striking time setting pin Over voltage detect pin with Shutdown Over voltage detect pin with timer latch Supply voltage input NMOS FET driver (New Function) NMOS FET driver
Lot No.
8 9 10 11 12
SOP-24 (Unit:mm)
13 14 15 16 17
Block Diagram
18 19 20 21 22 23 24
REV. B
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NOTE FOR USE
. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum ratings. . The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. . Mounting failures, such as misdirection or miscounts, may harm the device. . A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND pin. ALL Pin Voltage should be under VCC voltage +0.3V even if the voltage is under each terminal ratings. . BD9270F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. . When modifying the external circuit components, make sure to leave an adequate margin for external components actual value and tolerance as well as dispersion of the IC. . About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. . Under operating CP charge (under error mode) analog dimming and burst dimming are not operate. 10. Under operating Slow Start Control (SS is less than 1.5V), It does not operate Timer Latch. 11. By STB voltage, BD9270F are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.82.0V). 12. The pin connected a connector need to connect to the resistor for electrical surge destruction. 13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin.
Resistance (PinA) (PinB) C Transistor (NPN) B E GND P P N P substrate GND Parasitic diode N P P substrate GND Parasitic diode (PinB) (PinA) B Parasitic diode GND Other adjacent components Parasitic diode
N
N
C E GND
Fig-1 Simplified structure of a Bipolar IC
REV. B
Notice
Notes
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